1. Technical Field
The present invention relates to a DLL (delay locked loop) circuit and a method of controlling the DLL circuit, and more specifically, to a DLL circuit which performs a stable operation regardless of variations in the voltage level of a DLL power supply, and to a method of controlling the same.
2. Related Art
In general, a DLL circuit is used to provide an internal clock having a phase which leads the phase of a reference clock obtained by converting an external clock by a predetermined amount of time. In general, the internal clock is generated so as to operate in synchronization with an external clock in a semiconductor memory apparatus, such as a synchronous dynamic random access memory (SDRAM) having a considerably high degree of integration.
More specifically, if an external clock is inputted into to a clock buffer, the clock buffer generates an internal clock. Then, the internal clock controls a data output buffer that outputs data. In this case, the internal clock is delayed by a predetermined amount of time from the external clock by the clock buffer, and output data from the data output buffer is also delayed by a predetermined amount of time from the internal clock. Therefore, the output data is considerably delayed.
In order to solve the above-mentioned problem, a DLL circuit is used to make the phase of the internal clock lead the phase of the external clock by a predetermined amount of time such that the output data is not delayed with reference to the external clock. That is, the DLL circuit receives an external clock and generates an internal clock having a phase which leads the phase of the external clock, and the internal clock is used as a reference clock in, for example, a data output buffer.
Hereinafter, a DLL circuit according to the related art will be described with reference to the accompanying drawing.
FIG. 1 is a block diagram illustrating the structure of a DLL circuit according to the related art.
As illustrated in FIG. 1, the DLL circuit includes: an input control unit 1 for generating a buffer enable signal bfen from a clock enable command (hereinafter, signal CKE); a clock buffer 20 for buffering an external clock clk_ext according to the control of the buffer enable signal bfen so as to generate an internal clock clk_int; a delay unit 30 for delaying the internal clock clk_int in response to the input of a delay control signal dcl to generate a delayed clock clk_dly; a preliminary duty cycle correcting unit 40 for receiving the delayed clock clk_dly and dividing the delayed clock clk_dly into a rising clock rclk and a falling clock fclk; a duty cycle correcting unit 50 for correcting a falling edge time difference between the rising clock rclk and the falling clock fclk and generating an output clock clk_out; a delay compensating unit 60 for delaying the output clock clk_out to compensate for the delay time of the output clock clk_out caused by delay elements existing on a transfer path to the outside of a semiconductor integrated circuit, thereby generating a feedback clock clk_fb; a clock dividing unit 70 for dividing the frequency of the internal clock clk_int at a predetermined rate so as to generate a reference clock clk_ref, a phase comparing unit 80 for comparing the phase of the reference clock clk_ref with the phase of the feedback clock clk_fb; and a delay control unit 90 for generating the delay control signal dcl on the basis of the comparison result of the phase comparing unit 80, to control the delay time which is given to the internal clock clk_int by the delay unit 20.
In a semiconductor integrated circuit having the DLL circuit, in order to reduce power consumption, a power down mode is utilized to cut off the power supply to each region of the semiconductor integrated circuit. The operation of the clock buffer 20 during power down mode is controlled by input control unit 1. Input control unit 1 receives signal CKE and, as a result, generates buffer enable signal bfen. When the buffer enable signal bfen is received by the clock buffer 20 it outputs the internal clock clk_int. In the power down mode, the buffer enable signal bfen is disabled and the clock generating operation of the clock buffer 20 in the semiconductor integrated circuit having the DLL circuit stops.
Before the semiconductor integrated circuit having the DLL circuit enters the power down mode, a DLL power supply, which supplies voltage to each element of the DLL circuit, has a voltage level lower than an external power supply voltage. However, when the semiconductor integrated circuit having the DLL circuit enters the power down mode, the operation of each element stops and thus the whole load is reduced, which causes the voltage level of the DLL power supply to rise up to the level of the external power supply.
FIG. 2 is a timing chart that explains the operation of the DLL circuit according to the related art.
FIG. 2 shows a case in which, when the semiconductor integrated circuit having the DLL circuit enters the power down mode by receiving the signal CKE applied from the outside, the level of the DLL power supply Vdll rises. FIG. 2 also shows the reference clock clk_ref, the rising clock rclk, the falling clock fclk, and the output clock clk_out, which are locked by a delay locking operation of the DLL circuit. In this case, the rising clock rclk and the falling clock fclk are clocks that are output from the preliminary duty cycle correcting unit 40 and then input to the duty cycle correcting unit 50, and the output clock clk_out is a clock which the duty cycle correcting unit 50 outputs by correcting the duty cycles of the rising clock rclk and the falling clock fclk.
After the semiconductor integrated circuit having the DLL circuit enters the power down mode, the reference clock clk_ref, the rising clock rclk, the falling clock fclk, and the output clock clk_out are no longer generated by the DLL circuit. Whether the semiconductor integrated circuit enters the power down mode is determined, according to the buffer enable signal bfen output from the input control unit 1 operated by the signal CKE. The buffer enable signal bfen controls the operation of the clock buffer 20.
After the semiconductor integrated circuit exits the power down mode, the DLL circuit operates again to generate the reference clock clk_ref, the rising clock rclk, the falling clock fclk, and the output clock clk_out. When the semiconductor integrated circuit exits the power down mode, the DLL circuit starts to generate the clocks simultaneously. The voltage level of the DLL power supply Vdll rises as compared to a point in time when the voltage level of the DLL power supply Vdll is locked before the semiconductor integrated circuit enters the power down mode, and thus the delay values of the delay elements vary. Therefore, the variation causes an adverse effect in that the rising edge times of the reference clock clk_ref, the rising clock rclk, the falling clock fclk, and the output clock clk_out do not correctly correspond to one another.
As described above, the adverse effect occurring after the semiconductor integrated circuit exits the power down mode makes it difficult to correct a duty cycle of each clock and to set a clock locking reference point, thereby resulting in deterioration of the performance of the DLL circuit. In order to improve the performance of the DLL circuit, the above-mentioned malfunctions should be overcome, however, the related art has a technical limitation that cannot easily overcome the above-mentioned malfunctions.